lvalue lowering of cast to logic [31:0] not yet supported

[mdko]

I was trying to compile the following example code found in the PLDI paper:

module acc_tb;
    bit clk, en;
    bit [31:0] x, q;
    acc i_dut (.*);

    initial begin
        automatic bit [31:0] i = 0;
        en <= #2ns 1;
        do begin
            x <= #2ns i;
            clk <= #1ns 1;
            clk <= #2ns 0;
            #2ns;
            check(i, q);
        end while (i++ < 1337);
    end 

    function check(bit [31:0] i, bit [31:0] q);
        assert(q == i*(i+1)/2);
    endfunction
endmodule

module acc (input clk, input [31:0] x, input en, output [31:0] q);
    bit [31:0] d, q;
    always_ff @(posedge clk) q <= #1ns d;
    always_comb begin
        d <= #2ns q;
        if (en) d <= #2ns q+x;
    end
endmodule

However, when I do so, moore produces the following error:

❯ LLHD-Testing master* moore acc.sv -e acc_tb
compiler bug: lvalue lowering of cast to `logic [31:0]` not yet supported: Domain(FourValued)
  --> acc.sv:27:19-20:
   | 
   |     output [31:0] q
   |                   ^
   = note: Encountered at src/svlog/mir/lower/lvalue.rs:310

You have encountered a compiler bug. Sorry about that! We would appreciate if you open an issue [1] and describe how you triggered the bug, together with a minimal snippet of code to reproduce it. Thanks!
[1]: https://github.com/fabianschuiki/moore

thread 'main' panicked at 'lvalue lowering of cast to `logic [31:0]` not yet supported: Domain(FourValued)', /Users/michael/LLHD-Testing/moore/src/svlog/mir/lower/lvalue.rs:310:17
note: run with `RUST_BACKTRACE=1` environment variable to display a backtrace

I am using version 0.12.0 of Moore, compiled from the master branch.

I've also tried using the version of the Moore compiler included in the PLDI artifact, but it also produces an (albeit different) error on this example. I imagine this has been fixed since that version since I don't see it with the current version of Moore, but I include it here in case it's at all helpful:

root@c9ad6c8cf46d:/home/root# moore acc.sv -e acc_tb
thread 'main' panicked at 'internal error: entered unreachable code: compiler bug: implicit type not resolved
  --> acc.sv:24:5-11:
   |
   |     input clk,
   |

[thebyrd]

I also ran into this issue.

STDOUT

➜   moore --version
moore 0.12.0
➜   moore example.v -e std_fp_sdiv_pipe 

compiler bug: lvalue lowering of cast to `logic unsigned [31:0]` not yet supported: Sign(unsigned)
  --> systolig.v:297:20-30:
   | 
   |     .out_remainder(comp_out_r)
   |                    ^^^^^^^^^^ 
   = note: Encountered at /Users/davidbyrd/.cargo/registry/src/github.com-1ecc6299db9ec823/moore-svlog-0.12.0/mir/lower/lvalue.rs:310

You have encountered a compiler bug. Sorry about that! We would appreciate if you open an issue [1] and describe how you triggered the bug, together with a minimal snippet of code to reproduce it. Thanks!
[1]: https://github.com/fabianschuiki/moore

thread 'main' panicked at 'lvalue lowering of cast to `logic unsigned [31:0]` not yet supported: Sign(unsigned)', /Users/davidbyrd/.cargo/registry/src/github.com-1ecc6299db9ec823/moore-svlog-0.12.0/mir/lower/lvalue.rs:310:17
stack backtrace:
   0: _rust_begin_unwind
   1: std::panicking::begin_panic_fmt
   2: moore_svlog::mir::lower::lvalue::mir_lvalue
   3: moore_svlog::queries::QueryDatabase::mir_lvalue
   4: moore_svlog::codegen::UnitGenerator<&C>::emit_port_connections::{{closure}}
   5: <alloc::vec::Vec<T> as alloc::vec::spec_from_iter::SpecFromIter<T,I>>::from_iter
   6: moore_svlog::codegen::UnitGenerator<&C>::emit_port_connections
   7: moore_svlog::codegen::UnitGenerator<&C>::emit_module_block
   8: moore_svlog::codegen::CodeGenerator<&C>::emit_module_with_env
   9: moore::score
  10: moore::main

example.v

module std_fp_sdiv_pipe #(
    parameter WIDTH = 32,
    parameter INT_WIDTH = 16,
    parameter FRAC_WIDTH = 16
) (
    input                     clk,
    input                     go,
    input  signed [WIDTH-1:0] left,
    input  signed [WIDTH-1:0] right,
    output signed [WIDTH-1:0] out_quotient,
    output signed [WIDTH-1:0] out_remainder,
    output logic              done
);

  logic signed [WIDTH-1:0] left_abs;
  logic signed [WIDTH-1:0] right_abs;
  logic signed [WIDTH-1:0] comp_out_q;
  logic signed [WIDTH-1:0] comp_out_r;

  assign right_abs = right[WIDTH-1] ? -right : right;
  assign left_abs = left[WIDTH-1] ? -left : left;
  assign out_quotient = left[WIDTH-1] ^ right[WIDTH-1] ? -comp_out_q : comp_out_q;
  assign out_remainder = (left[WIDTH-1] && comp_out_r) ? $signed(right - comp_out_r) : comp_out_r;

  std_fp_div_pipe #(
    .WIDTH(WIDTH),
    .INT_WIDTH(INT_WIDTH),
    .FRAC_WIDTH(FRAC_WIDTH)
  ) comp (
    .clk(clk),
    .done(done),
    .go(go),
    .left(left_abs),
    .right(right_abs),
    .out_quotient(comp_out_q),
    .out_remainder(comp_out_r)
  );
endmodule