Is there a plan to support System Verilog features like Classes/Constraints/Interfaces?

[jainamq]

Hello,
We are exploring if Moore can be used to generate AST for the System Verilog Test Bench code as well. Is there a plan to support AST generation for Classes/Constraints/Interfaces?

Regards
Jainam

[fabianschuiki]

Hey @jainamq! Yes this is definitely a design goal of Moore. The parser doesn't really cover this part of the standard well at the moment, and there might be a few things that need to be added to LLHD and CIRCT to be able to fully capture what these parts of SV can do. Interfaces already work to some degree, mostly if you use them as signal bundle. But more advanced things like embedded tasks and declarations, and virtual interfaces, doesn't work yet.