Add amx to SPR's feature list #127
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From Intel's [manual](https://www.intel.com/content/www/us/en/content-details/836496/intel-architecture-instruction-set-extensions-programming-reference.html), the 3 supported CPUID bits are AMX-BF16, AMX-TILE, and AMX-INT8. From GCC's manual: ``` Intel Sapphire Rapids/Emerald Rapids CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW, AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2, VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB, MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512-FP16 and AVX512BF16 instruction set support. ``` As a side-effect, one test json previously recognized as SPR is now identified as ICX. Will need to update archspec's `test_cpu.py` list when update the submodule reference, if this is merged.
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@rscohn2 Can you comment on this one? Is it possible to turn off |
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From Intel's manual, the 3 supported CPUID bits are AMX-BF16, AMX-TILE, and AMX-INT8.
From GCC's manual:
As a side-effect, one test json previously recognized as SPR is now identified as ICX. Will need to update archspec's
test_cpu.pylist when update the submodule reference, if this is merged.