svlog: Fix ports with expl dir carrying over data

Fix an issue in the `port_list` module where a port with an explicit
direction would still carry over the previous port's type and sign. This
should instead reset everything to the default.

Fixes #224.

CHANGELOG.md

@@ -4,6 +4,8 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/), and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## Unreleased
+### Fixed
+- Fix ports with explicit direction carrying over previous port type data (#224)
 
 ## 0.12.0 - 2021-01-09
 ### Added

src/svlog/port_list.rs

@@ -462,15 +462,26 @@ fn lower_node_ports_ansi<'a>(
                 expr,
             } => {
                 // If no direction has been provided, use the one carried over
-                // from the previous port.
-                let dir = dir.unwrap_or(carry_dir);
+                // from the previous port. Explicitly specifying a direction
+                // clears the carried kind, type, sign, and packed dimensions to
+                // their defaults.
+                let dir = match *dir {
+                    Some(dir) => {
+                        carry_kind = None;
+                        carry_ty = Cow::Owned(ast::TypeKind::new(port.span(), ast::LogicType));
+                        carry_sign = ast::TypeSign::None;
+                        carry_packed_dims = &[];
+                        dir
+                    }
+                    None => carry_dir,
+                };
 
                 // If no port kind has been provided, use the one carried over
                 // from the previous port.
                 let kind = kind.or(carry_kind);
 
                 // If no port type has been provided, use the one carried over
-                //  from the previous port.
+                // from the previous port.
                 let (ty, sign, packed_dims, ty_span) = if ty.kind.data == ast::ImplicitType
                     && ty.sign == ast::TypeSign::None
                     && ty.dims.is_empty()

test/svlog/regr/iss224_port_type_carry.sv

@@ -0,0 +1,10 @@
+// RUN: moore %s -e A
+
+module A;
+  wire [31:0] x;
+  wire y;
+  B system_bus_xbar (.x(x), .y(y));
+endmodule
+
+module B (input [31:0] x, output y);
+endmodule