Non-constant case item not supported #227
Labels
A-codegen
Area: Code generation.
C-bug
Category: This is a bug.
E-help-wanted
Call for Participation: Help wanted on this issue.
L-vlog
Language: Verilog and SystemVerilog.
It seems like moore requires that case items evaluate to integer constants even though this is more restrictive than the SystemVerilog standard. For example, this code should be valid SystemVerilog:
But moore reports an error:
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