[wip] start application procelling #371
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hawkw
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Currently, some code in `hal-x86_64` depends on `liballoc`, while other code does not. This makes it difficult to use parts of the HAL crate in early boot environments without an allocator. This commit adds an "alloc" feature flag to `hal-x86_64`, which enables code that depends on `liballoc`. This commit was factored out of #371.
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Currently, TSS segments can only be constructed from statics. This makes it difficult to construct a TSS dynamically when bringing up an application processor. This commit adds a new `SystemSegment::boxed_tss` constructor, which allows TSS segments to be dynamically allocated, as well as stored in a static. This was factored out of PR #371.
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This commit adds support for the IA32_EFER model-specific register in the `hal-x86_64` crate's `cpu::msr` module. This includes a new `Efer` bitflags type representing the flags stored in the EFER register, and a `Msr::i32_efer` constructor for accessing the EFER. This is necessary for application processor bringup, and was factored out from PR #371.
hawkw
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Currently, some code in `hal-x86_64` depends on `liballoc`, while other code does not. This makes it difficult to use parts of the HAL crate in early boot environments without an allocator. This commit adds an "alloc" feature flag to `hal-x86_64`, which enables code that depends on `liballoc`. This commit was factored out of #371.
hawkw
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Currently, TSS segments can only be constructed from statics. This makes it difficult to construct a TSS dynamically when bringing up an application processor. This commit adds a new `SystemSegment::boxed_tss` constructor, which allows TSS segments to be dynamically allocated, as well as stored in a static. This was factored out of PR #371.
hawkw
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Nov 16, 2022
This commit adds support for the IA32_EFER model-specific register in the `hal-x86_64` crate's `cpu::msr` module. This includes a new `Efer` bitflags type representing the flags stored in the EFER register, and a `Msr::i32_efer` constructor for accessing the EFER. This is necessary for application processor bringup, and was factored out from PR #371.
hawkw
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Nov 16, 2022
Currently, some code in `hal-x86_64` depends on `liballoc`, while other code does not. This makes it difficult to use parts of the HAL crate in early boot environments without an allocator. This commit adds an "alloc" feature flag to `hal-x86_64`, which enables code that depends on `liballoc`. This commit was factored out of #371.
hawkw
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Nov 16, 2022
Currently, TSS segments can only be constructed from statics. This makes it difficult to construct a TSS dynamically when bringing up an application processor. This commit adds a new `SystemSegment::boxed_tss` constructor, which allows TSS segments to be dynamically allocated, as well as stored in a static. This was factored out of PR #371.
hawkw
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This commit adds support for the IA32_EFER model-specific register in the `hal-x86_64` crate's `cpu::msr` module. This includes a new `Efer` bitflags type representing the flags stored in the EFER register, and a `Msr::i32_efer` constructor for accessing the EFER. This is necessary for application processor bringup, and was factored out from PR #371.
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LOL THIS MAKES QEMU CRASH LMAO
```
[i] hal_x86_64::cpu::topology: initializing processor, self.id=0, self.state=Idle
[*] hal_core::mem: split_back, size=1024, self.size=2048, self.base=PAddr(0x7fd7800), self.addr=0xffff8080000122b0,
rem_size=1024, base=PAddr(0x7fd7c00)
[*] hal_core::mem: self=Region {
base: PAddr(0x7fd7800),
size: 1024,
kind: FREE,
}
[*] hal_x86_64::cpu::msr: rdmsr=MSR 0xc0000101 (IA32_GS_BASE), value=0x0
[*] hal_x86_64::cpu::local: initializing local data, ptr=0xffff818007fd7800
[*] hal_x86_64::cpu::msr: wrmsr=MSR 0xc0000101 (IA32_GS_BASE), value=0xffff818007fd7800
[i] mycelium_kernel::arch::x86_64: initialized boot processor
[i] mycelium_kernel::arch::x86_64: starting application processors
[i] ┌smp::bringup: bsp_lapic=LocalApic { msr: Msr(0x1b, IA32_APIC_BASE), base: VAddr(0xffff8180fee00000) }
[i] ├hal_x86_64::cpu::smp: AP trampoline: 0x8000 .. 0x8094
[i] ├hal_x86_64::cpu::smp: bringing up application processor... ap=Processor {
│ id: 1,
│ device_uid: 1,
│ lapic_id: 1,
│ is_boot_processor: false,
│ state: Idle,
│ }
[i] ├hal_x86_64::cpu::smp: sending INIT IPI to AP 1...
[?] │┌LocalApic::send_ipi: target=ApicId(1), kind=Init { assert: true }
[*] │├hal_x86_64::interrupt::apic::local: register=ICR_TARGET (0x310), write=IcrTarget {
││ APIC_ID: 1,
││ }
[?] │├hal_x86_64::interrupt::apic::local: sending IPI... flags=IcrFlags {
││ VECTOR: 0,
││ MODE: InitDeinit,
││ IS_LOGICAL: false,
││ SEND_PENDING: false,
││ INIT_ASSERT_DEASSERT: Assert,
││ DESTINATION: Target,
││ }
[*] │├hal_x86_64::interrupt::apic::local: register=ICR_FLAGS (0x300), write=IcrFlags {
││ VECTOR: 0,
││ MODE: InitDeinit,
││ IS_LOGICAL: false,
││ SEND_PENDING: false,
││ INIT_ASSERT_DEASSERT: Assert,
││ DESTINATION: Target,
││ }
**
ERROR:../accel/tcg/tcg-accel-ops-mttcg.c:110:mttcg_cpu_thread_fn: assertion failed: (cpu->halted)
Bail out! ERROR:../accel/tcg/tcg-accel-ops-mttcg.c:110:mttcg_cpu_thread_fn: assertion failed: (cpu->halted)
Error:
0: qemu exited with a non-zero status code
```
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